The present invention relates generally to fiber optic communications and in particular, to systems and methods for coupling photonic integrated circuits with integrated optical waveguides.
As optical fiber communication advances to handling larger bandwidth, optical or photonic integrated circuits (chips) with multiple input/output ports are expected to replace many of the discrete optical components that are currently interconnected using optical fibers to provide complex optical systems. Because the propagating light mode in a single-mode optical fiber is generally much larger than the beam size in a single-mode channel waveguide made from a semiconductor material such as silicon (Si) or compound semiconductors (e.g., AlGaAs, InGaAsP), it is necessary to transform the beam size between a fiber and an integrated semiconductor optical waveguide. Moreover, for maximally efficient coupling, the mode must be transformed from a circular shape in the fiber to an elliptical shape in the semiconductor waveguide. One existing technique for achieving relatively efficient beam size transformation is to place one or more discrete optical elements such as a micro-lens between the end faces of the fiber and the integrated optical waveguide. Obviously, this approach will not be cost-effective when the semiconductor based photonic chip has a large number of ports (e.g., more than 16).
An alternative is to fabricate an array of beam-size transformers together with an array of optical-fiber-positioning grooves (which typically have either a V-shaped or U-shaped cross section and will be referred to herein as V-grooves) on a single substrate using photolithography-based planar mass production means. Examples of such techniques are described in the above cross-referenced U.S. patent applications entitled “Integrated Planar Composite Coupling Structures for Bi-directional Light Beam Transformation between a Small Size Waveguide and a Large Size Waveguide” and “Connection Between A Waveguide Array And A Fiber Array.” This approach considerably reduces the difficulty of aligning and coupling the light path at the large-beam end of a beam-size transformer array with an optical fiber array.
At the small-beam-size end of the beam-size transformer, the light path must be aligned and coupled with the small-size channel waveguide of a photonic integrated circuit. In theory, the photonic integrated circuits could be fabricated together with the beam-size transformers and fiber-positioning V-grooves on the same substrate, thereby providing inherent alignment and connection. In practice, however, indium phosphide-based compound semiconductor (InGaAsP) is the only known usable material for fabricating active photonic circuits that provide light emission and detection at the most commonly used telecommunication wavelength band (about 1.3 μm to about 1.65 μm). Because indium-phosphide based materials are expensive and difficult to work with, single-substrate fabrication strategies are not practical for mass-production applications.
A more cost-effective approach takes advantage of the low-cost, well developed processing technologies for glass or silicon devices. Photonic integrated circuits (which are typically small) are fabricated on indium phosphide, while beam size transformers and fiber positioning V-grooves (which typically require a much larger surface) are fabricated together on a glass and/or silicon substrate. In such a system, the small-beam-size ports of the beam-size transformers must be aligned with the small channel waveguides of an InGaAsP-based photonic chip in order to provide efficient transmission of light. Various alignment systems have been used depending on the shape of the respective end faces of the photonic chip and the beam-size transformer.
For certain types of photonic devices, vertical end facets are desirable, e.g., semiconductor lasers (in which vertical end facets act as partially reflective mirrors to provide feedback for the laser cavity). Vertical end facets are easily created by cleaving the crystalline photonic substrate along its vertical crystal plane. Such devices are traditionally coupled to a fiber using discrete optical beam transforming components, e.g., a ball lens, to accomplish the beam-size and shape transformations.
To align photonic chips having vertical end facets with beam-size transformers and optical fibers, a recess may be dry-etched in the glass and/or silicon substrate on which the beam-size transformers and fiber-positioning V-grooves are formed or mounted, the size and depth of the recess being selected to provide alignment between the beam-size transformers and a photonic chip mounted in the recess. For example, Harpin et al., “Assembly of an optical component and an optical waveguide,” U.S. Pat. No. 5,881,190, issued Mar. 9, 1999, teaches that a recess may be formed on a SIMOX (Separation by IMplanted Oxygen) based silicon-on-insulator (SOI) substrate and used to mount and align a laser diode with a weakly guiding channel waveguide made on the same SOI substrate. Dry-etching of the recess provides vertical end walls matching the end facets of the photonic chip.
This method provides an alignment accuracy in the lateral and longitudinal directions determined by the limitations of photolithography (which has a feature size or position accuracy limit of about 0.5 microns), while vertical alignment is achieved by using a natural etch stop at the interface between silicon and SiO2 in the SOI wafer (which has a position accuracy limit of about 0.01 microns). The larger inaccuracy in the lateral direction is tolerable because for a III-V compound semiconductor-based channel waveguide, the guided beam mode is elliptical in shape. In general, the lateral beam size of a single-mode semiconductor waveguide is about two to three times the vertical beam size. For example, a weakly guided mode is typically about 5 μm wide by 2 μm high, and a strongly guided mode is about 1 μm wide by 0.4 μm high. Hence, the required precision of vertical alignment is higher than for lateral alignment.
But the recess technology has a number of limitations. For instance, the cleaving process cannot produce a photonic chip with a size controlled to submicron precision because of the relatively large size (typically a few microns) of the diamond tip that initiates the cleaving and the limited positioning precision (about 5 microns) of existing cleaving machinery. Further, existing automatic chip placement machinery offers a placement position accuracy of about 5 microns. Consequently, in order to allow for size variations in the cleaved photonic chips and to prevent mechanical damage to the photonic chip when it is placed into the recess, the recess must be made larger than the photonic chip by at least 10 microns. The photonic chip is then aligned with the channel waveguide by pushing the chip to one corner of the recess.
Thus, the method is limited to a photonic chip having only one output (or input) port on one side that must be connected and aligned with one channel waveguide. For photonic chips having input and output ports on both sides of the chip, as future applications will require, these designs are inadequate, in part because pushing a chip that is smaller (e.g., by 10 μm) than the recess to one end of the recess will always leave a gap (of 10 μm) at the opposite end, leading to unacceptable light loss at the opposite end.
Moreover, this method docs not address the need to flexibly control the depth of the recess to accommodate photonic chips of different waveguide dimensions. For example, Harpin discloses as a substrate a standard SIMOX-based SOI wafer in which the thickness of the buried insulating SiO2 layer has a standard value of approximately 0.4 μm. This insulating layer provides a natural etch stop, thereby defining the depth of the etched recess. If this standard thickness is not suitable for a particular configuration of photonic chip and integrated waveguide, then the technique of Harpin cannot be used.
For other types of photonic devices, such as amplifiers and modulators, vertical end facets are not desirable; end facets of these devices are typically made to have a small inclination angle (typically 8° or 9°) in the lateral plane so that reflected light does not couple back into the device. When the mounting recess has a vertical end wall, the coupling of the light path between the photonic device and the channel waveguide is not efficient.
Another design has been proposed for use with optical transceivers in which at least two single-function, single-port photonic chips, e.g., a laser diode and a photodiode, are mounted in trapezoidal U-grooves or wells wet-etched in silicon for coupling to an optical fiber. A layer of solder material in the bottom of the U-groove holds the chips in place. V-grooves in the silicon are used to position the optical fiber. Optionally, a micro-lens may be provided between the photonic chips and the optical fiber for beam-size transformation, or the optical fiber may simply be placed against the end face of the photonic chip. [E.g., M. H. Choi et. al., “Self-Aligning Silicon Groove Technology Platform for the Low Cost Optical Module,” 49th Electronic Components and Technology Conference, Jun. 2-4, 1999, San Diego, Calif., USA].
This approach also has limitations. Notably, because the fiber end face is vertical and flat, the end face of the channel waveguide must likewise be vertical and flat. Further, vertical alignment is provided by controlling the thickness of the solder material, which is imprecise. As a result, this arrangement provides precise alignment of the photonic chip and channel waveguide only in the lateral direction (transverse to the light propagation axis), not in the vertical direction.
An improved coupling system for photonic chips and integrated waveguides, suitable for use with multiport photonic chips, is therefore needed.